Multi-stage delay line using capacitor charge transfer



F. L. J. SANGSTER Dec. 8., 1970 MULTI-STAGE DELAY LINE USING CAPACITOR CHARGE TRANSFER Filed Oct. 17, 1967 10 Sheets-Sheet l FIG.2

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INVENTOR. FREDRIK LJ SANGSTER AGENT D c. 8 1970 F. L. J. SANGSTER 3,546, 90

MULTISTAGE DELAY LINE USING CAPACITOR CHARGE TRANSFER Filed Oct. 17; 1967 1O Sheets-Sheet 2 a 1 J f w m m H HM F MT E 0 r v T r i v Ft? 1 F T a G. nuir r TT FIG. 7b

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INVENTOR. FREOERIK L.J. SANGSTER FlG.7c

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AGENT Dec. 8, 1970 F. J. SANGSTER 3,546,490

MULTI-STAGE DELAY LINE USING CAPACITOR CHARGE'TRANSFER Fil ed Oct. 17, 1967 10 Sheets-Sheet s V I t FIG.9b T

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INVENTOR.

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. .MULTI-STAGE DELAY LINE USING CAPACITOR CHARGE TRANSFER Filed Oct. 17. 1967 Dec. 8., 1970 F. J. SANGSTER l0 Sheets-Sheet 4.

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INVENTOR. FREDERIK L.J. SAABSTER AGENTO Dec. 8 1970 F. L. J. SANGSTER 6,

MULTI-STAGE DELAY LINE USING CAPACITOR CHARGE TRANSFER Filed Oct. 17, 1967 7 1o Sheets-Sheet 5 INVENTOR. rnsosmn L. .1. sums rm M J T 4- AGENT Dec. 8., 1970 F. L. J. SANGSTER '1 1 ,49

MULTI-STAGE DELAY LINE USING CAPACITOR CHARGE TRANSFER Filed Oct. 17., 1967 v 10 Sheets-Sheet 6 a 1 T1 t 1 v E b S c 1 v E- d 1 v E. S

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' INVENTOR. FREDERIK |..J. SANGSTER AGENT Dec. 8, 1970 F. J. SANGSTER MULTI-STAGE DELAY LINE USING CAPACI [TOR CHARGE TRANSFER Filed Oct. 17', 1967 l0 Sheets-Sheet '7 FIG.15

INVENTOR. FREDERIK L.J. SANGSTER AGEN T Dec. 8, 1970 F, L. J. SANGSTER 3,

MULTI-STAGE DELAY LINE USING CAPACITOR CHARGE TRANSFER Filed Oct. 17, 1967 10 Sheets-Sheet 9 INVENTOR. rnsosmx L.J. SANGSTER AGENT Dec. 8., 1970 r--. L. J. SANGSTER 3,546,490

MULTI-STAGE DELAY LINE USING CAPACITOR CHARGE TRANSFER Filed Oct. 17, 1967 1'o Sheets-Sheet 1o I IINVENTOR. rnsosnm L.J. smasrsn w K-L$L AGENT United States Patent U.S. Cl. 307293 14 Claims ABSTRACT OF THE DISCLOSURE A multi-stage delay line where each stage a capacitor is connected directly across the base and collector terminals of a transistor. Each stage uses the transistor emitter for an input terminal, the collector for an output terminal, and the base as a control terminal for driving the transistor into conduction in response to a switching voltage applied to alternate stages.

This invention relates to a circuit for transferring charge from a first capacitor to a second capacitor by electronic switching means. The charge is supplied to the first capacitor by means of an input circuit. The charge is removed from the second capacitor by means of an output circuit.

This kind of a circuit is frequently used in capacitor memories and in delay lines, for example, audio-frequency or video-frequency signals. It is then necessary for the energy in a first capacitor to be transferred to a second capacitor with as little loss as possible.

In a known circuit of this kind an amplifier is included between a first capacitor and a second capacitor, said amplifier having a high input resistance and a low output resistance. In this circuit the second capacitor is first charged through a switch associated with it to the voltage. of the first capacitor. Subsequently the connection between the first and second capacitors is interrupted and the first capacitor is discharged through another switch associated with it. This known circuit suffers from the disadvantage that three operations are necessary for transferring the energy from the first capacitor to the second capacitor.

The present invention makes it possible to provide a circuit of the kind described which can be built up with considerably simpler elements and which is furthermore suitable to be integrated.

The invention is characterized in that a transistor is arranged between the first and the second capacitor, these capacitors being included in the emitter circuit and in the collector circuit respectively, while a switching voltage source which controls the transfer of charge is arranged between the connection of the second capacitor which is remote from the collector and the connection of the first capacitor which is remote from the emitter, said source being also included between the last-mentioned connection and the base of the transistor.

This circuit is preferably used in a devise for delaying electric signals, the device comprising succeeding circuits which are built up in the same manner so that in succeeding stages the second capacitor of the first stage is also the first capacitor of the second stage, and the second capacitor of the second stage is also the first capacitor of the third stage, etc.

In order that the invention may be readily carried into effect it will now be described in detail, by way of exam- 3,546,499 Patented Dec. 8, 1970 ple, with reference to the accompanying diagrammatic drawing in which:

FIG. 1 shows the circuit diagram of the inventionwhile FIG. 2 shows the variation in the voltage from the switching voltage source S of FIG. 1.

FIG. 3 shows a device for delaying electric signals for use of the circuit according to the invention while FIG. 5 shows the voltage variation at several points of the device as a function of time.

FIG. 4 shows the circuit which comprises the units of the FIGS. 6, 8, 12 and 17.

FIG. 6 shows another device for use of the circuit according to the invention, while FIG. 7 shows as a function of time the variations in the voltages from the switching voltage sources S S and S of FIG. 6.

FIG. 8 shows another device for use of the circuit according to the invention while FIG. 9 shows as a function of time the variations in the voltages from the switching voltage sources S S and S of FIG. 8.

FIG. 10 shows the circuit of a unit m which may replace at least one unit of the FIGS. 3, 6, 8, 12 and 17.

FIG. 11 shows the circuit of a unit 11 which may replace at least one of the units of the FIGS. 3, 6, 8, 12 and 17.

FIG. 12 shows another device for use of the circuit according to the invention while FIG. 13 shows as a function of time the variations in the voltages from the switching voltage sources 5 -8 and S S of FIG. 12.

FIG. 14 shows the device of FIG. 12 in which other input and output circuits are used.

FIG. 15 and FIG. 17 show a filter circuit for use of the device of FIG. 3 while FIG. 16 shows as a function of time the variations in the voltages from the switching voltage sources S S S and S of FIG. 15.

FIG. 18 shows the amplitude frequency characteristic of a comb filter.

FIG. 19 shows a dipole which may be arranged in parallel with one or more first capacitors in the stages 0 to n in the circuit according to FIG. 3.

In the circuit diagram of FIG. 1, T is an npn-type transistor, C is a first capacitor and C is a second capacitor. S is a switching voltage source which provides, for example, a voltage having the waveform shown in FIG. 2. From this figure it can be seen that the voltage between the base and ground is E volts during the time interval 7' and is 0 volt during the time interval 7' The switching voltage source S is included between the capacitors C and C The base of transistor T is connected to the connection of capacitor C which is remote from the collector. The voltage between the base of the transistor and ground is E volts during the time interval T The transistor will conduct as long as the voltage across the capacitor C is less than E volts, the base-emitter threshold voltage of transistor T being disregarded. A current will flow through the transistor which causes an increase in the voltage across the capacitor C,, and a decrease in the voltage across the capacitor C If the two capacitors are of the same value and if the collector-emitter current gain factor is assumed to be equal to unity, then the voltage across capacitor C will increase in the same period to the same extent as the voltage across capacitor C will decrease.

The output voltage across capacitor C will be E volts, since upon reaching this voltage the base-emitter junction of transistor T becomes cut-01f. Consequently the output voltage across capacitor C will be equal to (V -AV) volts, where AV is equal to the increase in voltage across capacitor C and where V,, is the voltage across capacitor C at the beginning of the transfer of charge between the two capacitors. When the voltage E volts is taken as a reference level for the information AV which was present in capacitor C the information AV has passed to capacitor'C while capacitor C has at the same time been charged to the reference level and hence is again in a condition for receiving new information from a preceding store element. Thus no separate switching operation is required for discharging capacitor C in order to bring it into a state for dealing with further information.

The device shown in FIG. 3 for delaying electric signals comprises a chain circuit of (n+1) stages each including a transistor with a capacitor arranged between its collector and its base. Such a stage as well as a symbolic view thereof are shown in FIG. 4. For the sake of clairity it is mentioned that the characters E, B and C of FIG. 1 correspond to the characters E, B and C of FIG. 4. In the further description E is the emitter input, C is the collector output and B is the base input of the stage considered. In FIG. 3, the collector output of each stage is D.C. connected to the emitter input of the succeeding stage, except for the (n+1) stage where the collector output is connected to the base input of the said stage. The output signal of the chain circuit is derived from the collector output of the 11 stage. The emitter input of the stage 0 is connected to ground through the series-combination of a resistor R and an input signal source V The base inputs of the even stages 0, 2, 4, etc. are connected to earth through the switching voltage source S whereas the base inputs of the odd stages 1, 3, 5, etc. are connected directly to earth.

For better understanding of the performance of the device of FIG. 3, the voltage waveforms at several points of this device are shown below one another as a function of time in FIG. 5. Graph a shows the voltage variation of the switching voltage source S It is a symmetrical square-wave voltage with +E volts at its maximum and E volts at its minimum, the period of the said squarewave voltage being equal to T sec. This period must be at least a factor of 2 smaller than the period of the highest signal frequency occurring in the input signal V which signal is shown in FIG 5b. During the time interval T0, T2, T4 and 1 point B of FIG. 3 has a potential of -E volts relative to point B The transistor T will not conduct during the said time interval if the input voltage is V E volts. In addition the even transistors T T etc. will not conduct since the voltages across the odd capacitors C C etc. can never exceed +E volts. The odd transistors will conduct during the same time intervals as long as the voltages across the even capacitors are less than B volts. The even capacitors are charged until their potential has become equal to E volts, while the voltage across each odd capacitor will decrease to the same extent as the voltage across the preceding even capacitor will increase. Thus it is assumed that all of the capacitors have the same value and that the collector-emitter current gain factor of each transistor is equal to unity.

During the period in which point B has a voltage of +E volts relative to point B information concerning the magnitude of the input signal V is transmitted to the capacitor C and hence during the time intervals T1, 1- 1- and T7 according to FIG. 5a-

The magnitude of the input signal during these time intervals is E, 0, +E and 0 volts respectively. During these time intervals a current will flow through the transistor T which is equal to (EV )/R +r maps, which current causes a decrease in the voltage of E volts, set up across capacitor C The currents flowing through the transistor T during thesaid time intevals are shown in FIG. 50, the behaviour of the voltage across capacitor C being shown in FIG. 5d. From the latter figure it can be seen that the voltage drops across capacitor C during the time intervals 7'1, 5- T5 and 1- vary linearly with time. This is true only if the resistor R has a value which is many times higher than the internal base-emittcr resistance of transistor T The greatest decrease in voltage occurs during the time interval T1, namely AV=E volts, while the voltage drop during the interval 1 is equal to 0 volt. Thus a linear relationship between the voltage drop AV across capacitor C and the input signal will exist only for input signals located in the range volts. The resistor R must be given a value such that, for an input signal of 0 volt, the voltage across capacitor C has become exactly equal to 0.5E volts during the period in which point B has a potential of +E volt relative to earth. The mean charging current i =E/R +r required therefore is determined by the value of capacitor C and the duration of each period T in which the potential of point B is equal to +E volts. The said charging current is equal to CUE/2T, wherein 0.5E is the voltage drop across capacitor C for an input signal of 0 volt. From this it follows that 1-:0.5.C .R must apply for correct adjustment of the mean charging current, referred to as zero adjustment. Advantageous values for the zero adjustment in connection with a satisfactory signal-to-noise ratio and the required switching power lie between 1 amp. and l m. amp.

The device of FIG. 3 can be used for delaying the'transit time of, for example, audio-frequency or videofrequency signals. The delay time per stage is then equal to 0.5 T sec. so that the total delay in transit time after the stage n will be equal to 0.5 (n+l)T. This transittime delay per stage can be raised by means of a device as shown in FIG. 6. This device includes three switching voltage sources S S and S arranged between earth and points B B and B respectively. The waveforms of the voltages provides by said switching sources are shown as a function of time in FIG. 7. Point B has a potential of +E volts relative to earth during the first /3 T sec. of each scan period T, which must be at least 2 times as small as the period of the highest signal frequency occurring, whereas points B and B have earth potential. During the succeeding /3 T sec. of each scan period T, point B has a potential of +E volts relative to earth, whereas points B and B have earth potential. During the final T sec. of each scan period, point B has a potential of +E volts relative to earth, whereas points B and B have earth potential. During this final /3 T sec. of each scan period information is transferred from the stage 0 to the capacitor C whilst there is no transfer of new information during /3 T sec. of each scan period. Thus the delay per stage has now become /3 T sec. so that the transit-time delay after the stage n will now be %.(n+1).T sec.

T sec.

However, p switching sources are now also required. Dependent upon the desired bandwidth and the total delay time which is desired, there will be a value for p at which the total number of stages required is a minimum.

FIG. 8 shows a device for delaying electric signals which has the advantage relative over the devices of FIG. 3 and FIG. 6 that, with the total delay time unchanged the losses occurring during the transfer of information between the capacitors are limited due to the collector emitter current gain factors not being exactly equal to unity. In this figure three congruent chains I, II and III are connected in parallel. The bases of the transistors in the stages III 1H 11,, I are connected to ground through the switching voltage source S The bases of the transistors in the stages III ,"II I and I are connected to ground through the switching voltage source S while the bases of the transistors in the stages I11 11 I1 I are connected to ground through the switching source S The emitter inputs of the first three stages I I1 and III are connected to a point of constant potential through the resistor R and the signal source V The collector outputs of the stages I II and III are connected together through blocking diodes D D and D respectively. The output comes with cyclic alternation from one of the stages I II and 111 while information is transferred to one of the stages I H and III likewise with cyclic alternation. It is thus achieved that the period of the squarewave voltages from the switching sources S S and S is allowed to be equal to 3T, where T is at least twice as small as the period of the highest signal frequency occurring. The said squarewave voltages have waveforms as shown in FIG. 9. Transfer of information takes place between two capacitors during 1 -3T sec.

of each period 3T, whereas no transfer of information takes place during 2 -3T see.

This means that the delay time per stage is equal to 2 -3T see.

so that three times femer stages in each of the chains I, II and III are necessary for obtaining a given total delay time. If in general It chains are connected in parallel similarly as has been effected for three chains in FIG. 8, the said losses can be reduced by a factor of 1/11.

By replacing at least one stage in the devices of FIG. 3, 6 or 8 by a stage In of FIG. 10 compensation for the previously mentioned losses is achieved. The stage In shown in this figure has an emitter input E which is connected to the emitter of a transistor T a base input B which is connected to the base of the transistor T and a collector output C which is connected through a diode D to the collector of the transistor T The collector of the transistor T is connected on the one hand through a capacitor C to the base of the transistor T and is connected on the other hand to the base of a transistor TR while the collector of the transistor TR is connected to a point of constant potential. The diode D is connected between the base and the emitter of the transistor TR The emitter of the transistor TR is connected through the capacitor C to the base of the transistor T and to the base of the transistor TR The emitter of the transistor TR is also connected to the collector of the transistor TR A diode D is provided between the base and the emitter of transistor TR while the emitter of transistor TR is connected to earth through the capacitor C The emitter input E of the stage In is connected to the collector output of the stage (m1). The collector output of the stage m is connected to the emitter input of the stage (m+1) while the base input of the stage In is connected to ground through the switching voltage source S which source supplies a voltage as is indicated in FIG. 5a. The base inputs of the two stages (m-l) and (m+1) are connected to ground. The operation of the stage 111 of the circuit of FIG. 10 is as follows:

During the time intervals T T2, T4 and T (FIG. 5a) the transistor T conducts and the capacitors C and C are charged until the voltage across these capacitors has become equal to E volt. The capacitor C is discharged during the mentioned time intervals through the diode D During the time intervals T1, T3, T5 and T7 (FIG. 5a) the transistor T conducts and the information V, which is present in the capacitor C is passed on to the capacitor C The output voltage across the capacitor C will then be equal to (E-AV) volt. During the latter time intervals the capacitor C is also discharged by the pump circuit (TR D C until the voltage across this capacitor has become equal to (E-AV) volt. During the time intervals succeeding the latter time intervals both the information AV present in the capacitor C and the information AV present in the capacitor C is passed on to the capacitor C The output voltage across the capacitor C will then be equal to:

in which C is the capacitance value of the capacitors C, and C Consequently, by providing the stage m between the stages (m1) and (m+1) of FIG. 10 it is achieved that the information V in the capacitor C amplified by a factor (l-il/ is passed on to the capacitor C For a good functioning of the stage in of the circuit of FIG. 10 it is necessary that C 20 so that the charge removed by the transistor TR is amply sufficient to be able to possibly fully discharge the capacitOI' C1.

It is also achieved that the mentioned losses remain limited or can be fully compensated by replacing at least one stage of the devices of FIGS. 3, 6 or 8 by a stage n of the circuit of FIG. 11. The stage n shown in the figure has an emitter input E, a base input B and a collector output C. The capacitor C is provided between the collector and the base of the transistor T The series combination of the capacitor C and the diode D on the one hand and the series combination of the capacitor C and the diode D on the other hand are provided parallel across this capacitor. The junction between the capacitor C and the diode D is also connected to the emitter of the auxiliary transistor TR while the junction between the capacitor C and the diode D is also connected to the collector of the auxiliary transistor. The base of the auxilary transistor is connected to the base of the transistor T The operation of the stage n of the circuit of FIG. 11 is as follows:

During the time intervals 7'0, 7'2, 7'4 and T6 of FIG. 5a the transistor T conducts and the capacitors C C and C are charged until the voltages across these capacitors have become equal to E volt. During the time intervals T1, T3, T5 and T7 of FIG. 5a the capacitors C C and C are partly discharged. The voltage drop Ax across the capacitors C and C will be equal to:

Ax -AV volt L C C1 in which C is the capacitance value of capacitors C C and C and in which V is the voltage difference between the voltages across the capacitors C and C during the time intervals To, T2, T4 and T6. The voltage drop across the capacitor C is equal to in which C is the capacitance value of the capacitors C C and C Consequently, by providing the stage n between the stages (n1) and (n+1) of FIG. 11 it is achieved that the information AV in the capacitor C amplified by a factor (l+C /C +C) is passed on to the capacitor C For a good functioning of the stage n of the circuit of FIG. 11 is necessary that C C because -AV volt otherwise the voltage across the capacitor C will decrease more rapidly than the voltage across the capacitor C As a result the diode D will start conducting, which is undesirable.

It is also achieved that the mentioned losses in the circuit according to FIG. 3 remain limited or can fully be compensated by arranging a dipole in parallel with one or more of the first capacitors in the stages 0 to n. This dipole comprises the series-combination of a diode which conducts during the transfer of charge and an addi tional capacitor which constitutes the output impedance between the emitter and the collector of an auxiliary transistor, the base-emitter path of which is connected in parallel opposition to the said diode, the junction of the diode and the base of the auxiliary transistor being connected to that side of the first capacitor from which the charge for the second capacitor is derived. In FIG. 19 the dipole is shown between the broken lines. The voltage source E provides the charge current for the additional capacitor C. During the times of each scan period T in which point B has a potential of E volts relative to point B both capacitors C and C Will be charged until the voltage across each of them has become equal to E volts, no allowance being made for the internal base emitter threshold voltage of the transistors T and T During this period the transistor T is in the cut-off condition. During the times of each scan period T in which the transistor T conducts and the transistor T is cut-off, information will be passed from a preceding capacitor to the capacitor C A current will flow through transistor T and cause a voltage drop, across capacitor C In the first instance the voltage across capacitor C will remain equal to E volts but as soon as the voltage capacitor C has decreased the auxiliary transistor T, will become conducting so that the voltage across capacitor C will also decrease. If the voltage drop across capacitor C is assumed to be AV volts this means that the voltage drop across capacitor C is equal to AV volts, no allowance being made for the internal base-emitter threshold voltage of the auxiliary transistor T,. If, now, transistor T commences to conduct the information AV from the capacitors C and C will be passed to the capacitor C which has a value equal to that of capacitor C If the collectoremitter current-gain factor of transistor T is assumed to be equal to unity and the internal base-emitter threshold voltage of auxiliary transistor T, is disregarded, then during the time in which transistor T conducts the voltage across capacitor C will decrease by an amount of (1+C/C AV volts. Thus the amplification of the information AV is equal to the factor (1+C/C If, for

example, C is 240 pfs. and C =C =200 pfs., the amplification of the information is equal to a factor of 2.2.

In FIG. 12, X and X are two identical units which are variants of the device of FIG. 8. These units X and X have, however, the advantage that they can be con-l nected in cascade without further external connections. This is especially important when integrating such units in which the mutual dividing and combining again of the parallel circuits in each unit shown in FIG. 12 must take place as much as possible within the integrated circuit so that only two wires are necessary for the input and output of the electric signal to be handled. The portions of the device of FIG. 12 (G and G situated within the full lines are identical to the portion of the device of FIG. 8 situated within the broken lines. The junctions 1, 2 and 3 and the junctions 4, S and 6 of FIG. 12 correspond to the junctions B B B of FIG. 8. The junctions C C C and the junctions C C C of FIG. 12 correspond to the junctions C C C of FIG. 8. The input P of the unit X which connects the three inputs of the chain circuits 1, II and III is connected to a point of constant potential through the series combination of the resistor R and the signal voltage source V The outputs C C and C of the chain circuits I, II and Ill are connected to the emitters of the respective transistors T T and T while the collectors of these transistors are connected to the output circuit of the unit X The output terminal P of the unit X is connected on the one hand to the input of the identical unit X and on the other hand to earth through the series combination between the capacitor C and the switching voltage source S The supply junctions 1, 2 and 3 shown in FIG. 12 are connected to earth through the switching voltage sources S S and S respectively. The supply junctions 4, 5 and 6 shown in FIG. 12 are connected to earth through the switching voltage sources S S and S respectively. The output circuit P of the unit X is connected to earth through the series'combination between the capacitor C and the switching voltage source S The FIG. 13a to It show the voltages which are supplied by the switching voltage sources S to S S and S as a function of time.

During the time interval 1 of a switching cycle T the junctions 1 and A have a positive potential relative to earth. As a result the information regarding the magnitude of the input signal V, will be stored in the 0 stage of the chain circuit III (1) while the information stored in the n stage of the chain circuit I (l) is passed on to the auxiliary capacitor C through the transistor T During the time interval 7'2 of each switching cycle T the junctions 4 and B have a positive potential relativeto earth. As a result the information which is stored in the capacitor C during the time interval T1 will be passed on to the 0 stage of the chain circuit III (2) of the unit X During the time interval 1 of each switching cycle the information from the 11 stage of the chain circuit I (l) is passed on to the auxiliary capacitor C while this information is passed on again to the 0 stage of the chain circuit I (2) of the unit X during the time interval 7'4. During the time interval T5 of each switching cycle T the information from the 12 stage of the chain circuit II (1) is passed on to the auxiliary capacitor C while this information is passed on again to the 0 stage of the chain circuit II (2) of the unit X during the time interval 1 of each switching cycle T.

FIG. 14 shows a device for retarding electric signals which has the additional advantage relative to the devices of FIGS. 3, 6, 8 and 12 that the zero adjustment is independent of frequency which is especially important for the use of the device as a variable delay line. The device is built up of units of FIG. 12 in which only shows the units X and X The junctions 1, 2, 3 and A of the unit X are connected to earth in the manner shown in FIG. 12 through the switching voltage sources S S S and S The junctions 4, 5, 6 and B of the unit X are connected to earth in the manner shown in FIG. 12 for the unit X through the switching voltage sources S S S and S,,. For the sake of clarity of FIG. 14 the switching voltage sources are not shown in this figure. The input P of the unit X is connected on the one hand to earth through the capacitor C and on the other hand through the diode D to the emitter of the transistor T connected as an emitter follower the base of which is connected to a point of constant potential through the signal voltage source V The emitter of the transistor T is connected to the collector of the transistor T the base of which is connected to earth on the one hand and on the other hand through the diode D to the emitter of the transistor T The emitter of the transistor T is connected through the capacitor C to junction A which is connected to earth through the switching voltage source S The output P of the unit X is connected on the one hand to junction A through the diode D and on the other hand to the base of the transistor T The emitter of the transistor T is connected on the one hand to the base of the transistor T and on the other hand to the collector of the transistor T the base of which is connected to earth on the one hand and to the emitter of the transistor T through the diode D on the other hand. The emitter of the transistor T is connected through the capacitor C to junction B which is connected to earth through the switching voltage source S The emitter of the transistor T is connected to the base of the transistor T the emitter of which is connected to earth through the load resistor R. The collectors of the transistors T T and T and jointly connected to a point of constant potential.

At the instants when the junction A of the capacitor C has a positive potential relative to earth (FIG. 13g) the transistor T is not conducting and the capacitor C is charged until the voltage across this capacitor has become equal to E volt as is indicated in FIG. 14. At the mentioned instants one of the junctions 1, 2 or 3 has also a positive potential relative to earth so that the transistor is conducting in one of the stages of the unit X (FIG. 12) so that the information stored in the capacitor C is passed on to the capacitor which is situated in the conductive stage. The capacitor C is also charged at the mentioned instants until the voltage across the capacitor C has become equal to E volt. At the instants when the junction A of the capacitor C has the earth potential the transistor T is conductive as a result of the charge Q=C E stored in the capacitor C and hence the transistor T is also conductive. As a result charge from the capacitor C will flow away through the diode D namely so much charge until the voltage across the capacitor C has become equal to /2E+V volt, being the sum of the voltages between the DC. voltage source E and the signal voltage source V, between the base of the transistor T and earth. As soon as the voltage across the capacitor C has become equal to this /2 E V volt the diode D becomes non-conductive. The transistor T becomes non-conductive as soon as the transistor T is not conductive which takes place as soon as the capacitor C is fully discharged. For a good operation of the input circuit of FIG. 14 it is therefore necessary that C C The output circuit of the device of FIG. 14 which is formed by the transistors T T T and T the diode D the capacitor C and the load resistor R has the advantage on the one hand that it has such a high input resistance that the outputcapacitance C of the unit X is substantially not charged which is important at low switching frequencies (audio frequencies) and on the other hand it has the advantage that there is no distortion of the signal at high switching frequencies (video frequencies). The operation of the output circuit of FIG. 14 is as follows:

At the instants when the junction B of the capacitor C has a positive potential relative to earth the capacitor C is charged until the voltage across it has become equal to E volt as shown in FIG. 14. At the mentioned instants also junction B of the unit X has a positive potential relative to earth so that the information from one of the 22 stages of the unit X is passed on to the capacitor C of the unit X (see FIG. 12). At the mentioned instants the voltage between the base of the transistor T and earth is equal to (E+V. in which V is equal to the voltage across the capacitor C of the unit X This voltage is equal to that across the load resistor to the neglect of the base emitter threshold voltages of the transistors T T and T The input impedance of the output circuit at the mentioned instants is approximately equal to 5 R in which 6 is the collector base current gain factor of the transistors T T and T At a [3:100 and a R=1000t2 this results in an input impedance of 1,000 M52 which is connected parallel across the capacitor C of the unit X At the instants when the junction A of the diode D; has a positive potential relative to earth, while the junctions B of the unit X and the capacitor C have the earth potential, the diode D is conductive so that the capacitor C of the unit X is charged until the voltage across this capacitor has become equal to E volt. Since the junction B of the capacitor C has the earth potential at these instants the transistor T becomes conductive as a result of the charge Q C E stored in the capacitor C As a result the charge in the stray capacitance between the base and the emitter of the transistor T together with the charge of the total stray capacitances between the emitter of the transistor T and earth, can flow away rapidly which results in the voltage drop at the base of the transistor T being followed very rapidly by the emitter of the transistor T so that no distortion of the signal to be retarded occurs at high switching frequencies.

The delay line shown in FIG. 3 can be used with advantage to realize a filter for electric signals as is indicated in the FIGS. 15 and 17. In the filter shown in FIG. 15 the connection ends of the second capacitors adjacent the collector from the delay stages 1, 3, 5 and 7 are connected to a combination device which is formed by the transistor T22, T and T the diodes D D D and D and the capacitors C11, C33, C55, C77, C3, C9 and C10. The connection ends of the said second capacitors remote from the collector are jointly connected to a point of constant potential. The collectors of the transistors T and T are connected through the capacitors C and C respectively to the emitter of the transistor T the base of which is connected to earth while the diode D is connected antiparallel across the base emitter path of this transistor. The collectors of the transistors T and T are connected through the capacitors C and C respectively the base of which is connected to earth while the diode D is connected antiparallel across the base emitter path of this transistor. The collector of the transistor T is connected on the one hand to earth through the capacitor C and on the other hand to the emitter of the transistor T the base of which is connected to earth through the switching voltage source S and the collector of which is also connected to earth through the series combination of the diode D and the switching voltage source S The collector of the transistor T is connected to earth through the series combination of the diode D and the switching voltage source S The output U of the filter is connected to earth through the capacitor C on the one hand and to the collector of the transistor T on the other hand while the output is connected to the collector of the transistor T through the capacitor C During the time intervals 1 T and 7' of FIG. 16 new information regarding the magnitude of the input signal is stored in the capacitor C The information stored in the odd capacitors C C and C is passed on to the even capacitors C C and C charge being supplied to the odd capacitors during the mentioned time intervals until the voltage across these capacitors has become equal to E volts. During these time intervals a voltage of +2E volt is present between the base of the transistor T and earth, a voltage of +2E volt between the diode D and earth and a voltage of zero volt between the diode D and earth. The transistors T T and the diode D are conductive during the mentioned time intervals. The capacitors C C C and C are charged until the voltage across these capacitors has become equal to E volt While the capacitor C3 is charged until the voltage across this capacitor has become equal to 2E volt. The amount of charge which will flow through the capacitor C during, for example, the time interval r will be equal to wise the charge which will fiow through the capacitor C during the mentioned time interval will be equal to in which C -AV (1-) is the charge which was necessary 1 1 1 seconds earlier, thus during the time interval To, to make the voltage across the capacitor C equal to E volt. If the capacitance values of the capacitors C to C are equal to C then this means that during the time interval 1 the capacitor C receives a supply of charge through the transistor T which is equal to In the given example of FIG. 15 the junction A of the combination device is only connected through the capacitors C and C to two junctions of the delay line of FIG. 15. By extension of the number of delay stages this number can be increased without further which is indicated in the Equation 1 by an additional symbol.

During the time interval To a voltage of -2E volt is present between the diode D and earth according to FIG. 16, a voltage of +4E volt between the diode D and earth While the base of the transistor T has the earth potential. The capacitor C will be charged through the diode D until the voltage across this capacitor has become equal to 4B volt while the capacitor C is charged through the diodes D and D until the voltage across this capacitor has become 6E volt. During the time interval To the capacitors C and C are charged until the voltage across these capacitors has become equal to E volt. The charge C.AV necessary for this purpose for the capacitor 0.; will flow through the two capacitors C and C and the voltage across the latter two capacitors will decrease to an amount equal to The charge which consequently flows through the capacitor C is equal to C .Ax. The charge C.AV necessary for this purpose for the capacitor C will flow through the two capacitors C and C and will decrease the voltage across the latter two capacitors by an amount equal t0 A =-AV The charge which consequently flows through the capacitor C is equal to C /Ay. The sum of the charges C .Ax and C .Ay is derived from the charge of the capacitor C That sum is thus equal to During the time interval 7'1, thus 1' seconds later, the capacitor C is charge until the voltage across this capacitor has become equal to 2E volt. The amount of charge required for this purpose is derived from the capacitor C The charge which is derived from the capacitor C is thus equal to in which C.AV (-r) is the charge which was necessary T second earlier to make the voltage across the capacitor C equal to E volt and C.AV6(T) is the charge which was necessary 7' second earlier to make the voltage across the capacitor C equal to E volt. In the given example of FIG. and junction B of the combination device is only connected to two junctions of the delay line. By extension of a number of delay stages this number can be increased. The total charge which flows through the capacitors C during the time interval 7 considered is equal to If it is assumed that the analogous signal supplied by the signal voltage source V comprises a spectrum component of angular frequency w and amplitude A then AV.e can be written in complex writing for the voltage drop AV across the capacitor C in which AV is directly proportional to the amplitude A of the spectrum component considered. In succeeding delay stages the relevant spectrum component is passed on over periods '1', 2T, 3T, 4T, 57-, 6T, 71- which spectrum component passed over this period can be Written as In the Formula 4 for the total charge which flow through the capacitor C there applies By filling in the above-mentioned equations in Formula 4 by subsequently arranging and by dividing by C the voltage drop across the capacitor C is found as a function of time.

A random spectrum component AV.e in the frequency spectrum of the signal supplied to the capacitor C yields an output signal as in Formula 5 so that for the transfer characteristic I-I(w) of the device formed by the delay line from the capacitor C and the combina tion device we have:

By suitable choice of the transfer coeflicients a :1 b b a random amplitude frequency characteristic and phase frequency characteristic can be realized.

In the filter of FIG. 17 the connection ends of the second capacitors adjacent the collector from the delay stages 1, 3, 5 and 7 are connected to a combination device which is formed by the transistors T T T T T T77 and the resistors R R R R R. The connection ends of the said secondcapacitors are connected to the base electrodes of the n-p-n transistors T T T and T respectively. The collector electrodes of the transistors T u and T are connected to the base of the p-n-p transistor T The emitter electrodes of the transistors T and T are connected through the resistors R and R respectively to a point of constant potential. The collector of the transistor T is connected through the output resistor R to a point of constant potential while the emitter of the transistor T is also connected to a point of constant potential. The collector electrodes of the transistors T and T are connected to a point of constant potential while the emitter electrodes of the transistors T and T are connected through the resistors R and R respectively to the base of the n-p-n transistor T the collector of which is connected to the collector transistor T while the emitter is connected to a point of constant potential.

If it is assumed that the analogous signal supplied by the signal voltage source V comprises a spectrum component of angular frequency w and amplitude A then AVJZ can be written in complex writing for the voltage drop AV across the capacitor C from the delay stage 0 in which AV is directly proportional to the amplitude A of the spectrum component considered. In succeeding delay stages 1, 2, 3, 4, 5, 6, 7 the relevant spectrum component is passed on over periods '1', 27', 31-, 41, 51', 71- which components passed over this period can be written as As a result of the signal AV.e at the base of the transistor T and the signal AV.e at the base of the transistor T a base current will fiow through the transistor which is equal to AV AV iw(t iw(t-31) l l" 3 R1 8 +R2 e As a result of the signal AV.e at the base of the transistor T and the signal AV.e at the base of the transistor T a base current will flow through the transistor T which is equal to AV AV iw(t-5 iw(t7-r) s-l' v R3 6 l' 6 (8) A current will now flow through the output resistor R which is equal to the difference between the currents of Formulas 7 and 8 so that the increase of voltage AV(R) across this resistor will be equal to iw i.. iw 3 4 A random spectrum component AV.e in the frequency spectrum of the signal supplied to the capacitor C yields an output signal such as in Formula 9, so that for the transfer characteristic H(w) of the device we have:

H( fl. j 41 i\v31'+ eiWT+ b iw ,32-6 in a /R GQZR/RZ b /R and b2'= /R4- By suitable choice of the transfer coeflicients a a b b a random transfer characteristic can be realized.

By providing a feedback between the collector output of the delay stage n and the emitter input of the delay stage 0 and the omission of the stage (n+1) of FIG. 3 another type of filter for electric signals can be realized. If the transfer function of the delay line is equal to then by providing said feedback the transfer function becomes equal to The amplitude frequency characteristic has a comb-like form with adjustments which are given by the condition exp(jwr)=1. This characteristic is shown in FIG. 18. If the delay line of FIG. 3 comprises 11 capacitors and if the passing-on frequency is equal to HLW. then the fundamental frequency of the comb filter becomes equal to w What is claimed is:

1. A delay line for delaying input signals from a signal source, comprising a source of switching pulses; a plurality of capacitor-charge transfer stages; each of said stages comprising a separate transistor having emitter, collector and base terminals, and a storage capacitor connected directly in parallel with the base and collector terminals, wherein the emitter and base terminals of the transistor respectively comprise the input and control terminals of each stage, and wherein the collector terminal of the transistor is connected to the output terminal of each stage; means for connecting each input terminal of all but a selected stage to the output terminal of an adjacent stage including the output terminal at the selected stage, the selected stage comprising the input stage of the delay line, the stage remote from the input stage comprising the output stage of the delay line; and means for applying a forward biassing switching pulse sequentially to the base terminals of adjacent stages, means for applying input signals to the input terminal of the input stage from the input signal source, the capacitor of the input stage attaining a charge corresponding to the level of the input signal on the input terminal thereof in response to the switching pulse on the control terminal thereof, the capacitor of each stage passing the charge level thereon to the adjacent stage connected to the output terminal thereof in response to a switching pulse on the control terminal of the adjacent stage.

2. Apparatus as claimed in claim 1, further including a resistor connected in series between the input signal and the input terminal of the input stage of the delay line.

3. Apparatus as claimed in claim 1, wherein said input signal applying means comprises a first capacitor connected intermediate the input terminal of the input stage of the delay line and a point of constant potential, a first diode connected to the side of the first capacitor remote from the point of constant potential, a first auxiliary transistor having base, emitter and collector terminals, means for connecting the base and collector terminals of the first auxiliary transistor across the combination of the first diode and first capacitor, a second diode connected in parallel with the base and emitter terminals of the first auxiliary transistor, the first and second diodes and the collector-emitter path of the first auxiliary transistor forming a conduction path across the first capacitor wherein each element of the conduction path is polarized in the same direction, a second capacitor, means for connecting the second capacitor intermediate the switching pulse applying means and the emitter of the first auxiliary transistor, a second auxiliary transistor having base, emitter and collector terminals, and means for connecting input signals from the input signal source to the side of the first diode remote from the first capacitor through the base emitter path of the second auxiliary transistor, the collector of the second auxiliary transistor being biassed in the forward direction.

4. Apparatus as claimed in claim 1, further comprising an additional transistor, means for connecting the emitter of the additional transistor to the output terminal of the stage most remote from the input stage, and means for connecting the base and collector terminals of the additional transistor to the control terminal of the input stage of the delay line.

5. Apparatus as claimed in claim 1, further comprising a cascaded series of transistors, a resistor, means for connecting the output terminal of the stage most remote from the input stage to the resistor through the base and emitter terminals of the cascaded series of transistors, an auxiliary transistor, means for connecting the collector of the auxiliary transistor to the emitter of the transistor in the cascaded series most remote from the resistor, a diode connected in parallel with the base and emitter terminals of the auxiliary transistor, an auxiliary source of switching pulses, an auxiliary capacitor and means for connecting the emitter of the auxiliary transistor to the auxiliary source of switching pulses through the auxiliary capacitor.

6. Apparatus as claimed in claim 1, wherein at least one of the stages further comprises, a first auxiliary capacitor connected to the output terminal of the one stage, a first diode connected to the output terminal of the one stage, a second diode, means for connecting the side of the first auxiliary capacitor remote from the output terminal of the one stage to the control terminal of the one stage through the second diode, a second auxiliary capacitor, means for connecting the side of the first diode remote from the output terminal of the one stage to the control terminal of the one stage through the second auxiliary capacitor, an auxiliary transistor having base, emitter and collector terminals, means for connecting the base terminal of the auxiliary transistor to the control terminal of the one stage, means for connecting the emitter of the auxiliary transistor to the side of the second diode remote from the control terminal ofthe one stage, means for connecting the collector of the auxiliary transistor'to the sideof the first diode remote from the output terminal "of theone stage, the first andseconddiodes and the collector emitter path of the auxiliary transistor forming a conduction path between the output and control terminals. ofthe one stage -wherein each element of the. conduction path is polarizedfin'the same direction;

'7.. Apparatus .asclaimed in claim 1, wherein at' least oneloflthel stages further comprises an auxiliary tran- "'sistor having base, emitter and collector terminals, means for connecting; the base terminal-of the, auxiliary transistor to the outputterminaliof the one stage, means for connecting the collectorterminal of the transistor to the control terminahoflthebne stage, a diode con 16 12. Apparatus as' claimed in claim 10, wherein the combining means comprises a plurality of auxiliary capacitors, a first auxiliary transistor, means for connecting the output terminals of alternate stages of the delay line to. the emitter of .the first auxiliary transistor through the auxiliary capacitors, a first diode connected in paral lel with the base and emitter terminals of the first auxiliary transistor, an additional capacitor connected in parallel with the base and collectorterminal's of the first auxiliary transistor, a second auxiliary transistor, means for connecting the emitter of' the second auxiliary transistor to the collector of the first .auxiliary-..transistor, a first auxiliary switching pulse source 'connected to the base of the second auxiliary, transistor, a second .diode, a second auxiliary source of switching pulses operating in phase opposition with the first auxiliary switching source,

' 7 means for connecting the vsecondauxiliary switching nected inp'arallel with the baseand emitter terminals of the auxiliary transistor, an auxiliary capacitor, and means for connecting the emitter of the auxiliary transistor to the 'control terminal of the one'stage through the, auxiliary capacitor,. the diode and the collector emitter path of the auxiliary transistor forming a conduction path be- 7 tween the output and control terminals of theone stage wherein each element of the conduction path is polarized in the same direction.

8. Apparatus as claimed in claim 1, wherein the plu rality of stages comprises a series of cascaded groups of 11 ordered stages, wherein the switching pulse" source comprises a separate switching sourceflfor each nth stage of a group, wherein the separate switching pulse sources provide non coincident switching pulses sequentially proceeding from the stage most remote from the input stage to the input stage, andwherein the recurrence frequency of each source is at least twice that of the highest signal source frequency.

9. Apparatus as claimed in claim8, wherein the plurality of stages comprises n series of the cascaded groups, wherein the input terminal of the input stage of each series is connected to a common point, and wherein the switching pulse sources connected to the control terminals of the input stages of each series sequentially provide non coincident switching pulses vto each control terminal of the input stage ofeach series.

10. Apparatus as claimed in claim 1, for use as a filter for electric signals, further comprising means cOn nected to the output terminals of alternate stages for combining the output signals, wherein the repetition frequency of the, switching pulse source is higher than twice the frequency of the highest signal frequency-to be filtered.

lLApparatus as claimed in claim 10, wherein the combining means comprises an auxiliary transistor hav; ing base, emitter and coll ector terminals,.at least two auxiliary capacitors, means .for connecting one side of each auxiliary capacitorto the output terminal .of each separate alternate stage, 'm ea ns" for connecting the other pulse source to the collector of thesecond auxiliary transistor. through. the second diode, the collector of the second auxiliary transistor comprising the output terminal of the combining means.

13.. Apparatus as claimed in cla1m 12, wherein the combining'means 'further comprises a second plurality of auxiliary capacitors, a third'au'xiliary transistor, means for connecting the output terminals of alternate stages of the delay line through the second plurality of auxiliary capacitor to the "emitter terminal of the third auxiliary transistor, a third diode connected in parallel with the base and emitter terminals of the third auxiliary' transistor, a third auxiliary. switching pulse source providing switching pulses in phase opposition to' the output of the second auxiliary switching pulse source, a fourth diode, means for connecting the third auxiliary switching .pulse source to the collector of the third auxiliary transistor through the third diode, a series connected pair'of additional capacitors connected in parallel with the base and collector terminals of the third transistor, and means for connecting the junction of the series connected pair of additional capacitors to the output terminal of the combining means.

14 Apparatus as claimed in claim 10, wherein the com- 1 bining means comprises a plurality of auxiliary transisside of each: auxiliary capacitorto the emitter of the I auxiliary transistor, afirst diode connected in parallel with the base emitter terminals of the auxiliary transist'or, therfirst diode andthe base emitter terminals of the. auxiliary transistor being oppositely polarized, a second diode; anauxiliary source of switching pulses, rneans -f or .conn ec ting thefcollector of; the apxilia'ry tran- .s or h auxil r switching P l ou e h the second diode and a pair "of; series connected output capacitors connected in parallel with the base and col} l ector'jterminals of the auxiliary transistor; the output 0t ng means comprising the junction of the rmat connecting the other ends of the resistors to a reference voltage, or additional transistor of a conductivity type opposite that of the auxiliary transistors, means for connecting the collectors of the auxiliary transistors to the base of the additional transistor, means for connecting 'the emitter of the additional transistor to a reference voltage, an additional resistor, and means for connecting the collector of the additional transistor to a reference .voltage through the additional resistor.

References Cited UNITED STATES PATENTS i 3,058,012 10/1962 -Harling L 307227 3,207,923 9/1965 Prager 328186X 1 3,289,010 ll/1966- Bacon et a1. 30722l 3,411,018 11/1968 Dapper et-al. 307-,-235

3,443,190 5/ 1969 Christiansen 3.072 46X 

